1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device capable of electrical writing, reading, and erasing, and a manufacturing method thereof. In particular, the present invention relates to a structure of a charge storage layer in the nonvolatile semiconductor memory device.
2. Description of the Related Art
A market of nonvolatile memory capable of electrically rewriting data and storing data even when power is turned off has been expanded. The nonvolatile memory has a similar structure to that of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and has a feature in that a region capable of storing charge for a long period of time is provided over a channel formation region. This charge storage region is formed over an insulating layer and is insulated and isolated from a peripheral region; accordingly, the charge storage region is referred to as a floating gate. A control gate is provided over the floating gate with another insulating layer interposed therebetween.
In so-called floating gate type nonvolatile memory having such a structure, an operation in which charge is stored in a floating gate and the charge is discharged is performed by voltage applied to a control gate. That is, when the charge which is to be retained in the floating gate is taken in and out, data is stored. Specifically, the charge is injected into or extracted from the floating gate by application of high voltage between a semiconductor layer in which a channel formation region is formed and the control gate. It is said that, at this time, Fowler-Nordheim (F-N) type tunnel current (NAND type) or a thermoelectron (NOR type) flows through an insulating layer formed over the channel formation region. Accordingly, the insulating layer is also referred to as a tunnel insulating layer.
It is necessary for the floating gate type nonvolatile memory to have a characteristic of being able to retain charge stored in the floating gate for more than ten years in order to assure reliability. Therefore, it is necessary for the tunnel insulating layer to be formed to be thick enough to make tunnel current flow and to have a high insulating property so that the charge is not leaked.
In addition, the floating gate formed over the tunnel insulating layer is formed of silicon that is the same semiconductor material as that used for the semiconductor layer in which the channel formation region is formed. Specifically, a method in which the floating gate is formed of polycrystalline silicon has been common, and for example, a floating gate formed in such a manner that a polysilicon film is deposited to a thickness of 400 nm has been known (see Patent Document 1: Japanese Published Patent Application No. 2000-58685 (Page 7, FIG. 7)).